Renesas H8S Series Hardware Manual page 883

TGR3A—Timer General Register 3A
TGR3B—Timer General Register 3B
TGR3C—Timer General Register 3C
TGR3D—Timer General Register 3D
Bit
Initial value
Read/Write
TCR4—Timer Control Register 4
Bit
Initial value
Read/Write
: 15 14 13 12
: 1 1 1 1
: R/W R/W R/W R/W
: 7 6 5
— CCLR1 CCLR0
: 0 0 0
: — R/W R/W
Counter Clear
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting
the SYNC bit TSYR to 1.
H'FE88
H'FE8A
H'FE8C
H'FE8E
11 10 9 8 7
1 1 1 1 1
R/W R/W R/W R/W R/W
H'FE90
4 3 2
CKEG1 CKEG0 TPSC2
0 0 0
R/W R/W R/W
Timer Prescaler
0 0
1
1 0
1
Note: This setting is ignored when channel 4 is in phase
counting mode.
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
Note: This setting is ignored when channel
4 is in phase counting mode.
TPU3
TPU3
TPU3
TPU3
6 5 4 3 2
1 1 1 1 1
R/W R/W R/W R/W R/W
TPU4
1 0
TPSC1 TPSC0
0 0
R/W R/W
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
0 Internal clock: counts on ø/1024
1 Counts on TCNT5 overflow/underflow
Rev.6.00 Oct.28.2004 page 855 of 1016
1 0
1 1
R/W R/W
REJ09B0138-0600H