Dmac Single Address Mode And Dram Interface; When Dds = 1 - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

Hide thumbs Also See for H8S Series:

Table of Contents

Note: n = 2 to 5

Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0)

DMAC Single Address Mode and DRAM Interface

When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When

DRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed

is selected.

Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low

state in the case of the DRAM interface.

Figure 6-28 shows the DACK output timing for the DRAM interface when DDS = 1.

Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access)

CAS, (UCAS),

LCAS, (LCAS)

Note: n = 2 to 5

Rev.6.00 Oct.28.2004 page 149 of 1016

REJ09B0138-0600H