Renesas H8S Series Hardware Manual page 249

Full Address Mode (Block Transfer Mode): Figure 7-22 shows a transfer example in which TEND output is enabled
and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to
external 16-bit, 2-state access space.
ø
Address bus
RD
HWR
LWR
TEND
Bus release
Figure 7-22 Example of Full Address Mode (Block Transfer Mode) Transfer
A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is
released, one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is
inserted after the DMA write cycle.
One block is transmitted without interruption. NMI generation does not affect block transfer operation.
DMA DMA DMA DMA
read write read write
Block transfer
DMA DMA DMA DMA
dead read write read
Bus release Last block transfer
Rev.6.00 Oct.28.2004 page 221 of 1016
DMA DMA
write dead
Bus
release
REJ09B0138-0600H