Renesas H8S Series Hardware Manual page 911

DMATCR—DMA Terminal Control Register
Bit
DMATCR
Initial value
Read/Write
DMACR0A—DMA Control Register 0A
DMACR0B—DMA Control Register 0B
DMACR1A—DMA Control Register 1A
DMACR1B—DMA Control Register 1B
Full address mode
Bit
DMACRA
Initial value
Read/Write
: 7 6
: — —
0 0
:
: — —
: 15 14
: DTSZ SAID SAIDE
: 0 0
: R/W R/W
Source Address Increment/Decrement
0 0
1
1 0
1
Data Transfer Size
0 Byte-size transfer
1 Word-size transfer
H'FF01
5 4
TEE1 TEE0
0 0
R/W R/W
Transfer End Enable 0
0 TEND0 pin output disabled
1
TEND0 pin output enabled
Transfer End Enable 1
0 TEND1 pin output disabled
1
TEND1 pin output enabled
H'FF02
H'FF03
H'FF04
H'FF05
13 12 11
BLKDIR BLKE
0 0 0
R/W R/W R/W
Block Direction/Block Enable
0 0
Transfer in normal mode
1 Transfer in block transfer mode, destination side is block area
1 0
Transfer in normal mode
1
Transfer in block transfer mode, source side is block area
MARA is fixed
MARA is incremented after a data transfer
MARA is fixed
MARA is decremented after a data transfer
DMAC
3 2 1
— — —
0 0 0
— — —
DMAC
DMAC
DMAC
DMAC
10 9 8
— — —
0 0
0
R/W R/W R/W
Reserved
Only 0 should be written to this bit.
Rev.6.00 Oct.28.2004 page 883 of 1016
0
—
0
—
REJ09B0138-0600H