Renesas H8S Series Hardware Manual page 331

Port A Data Register (PADR)
Bit : 7
PA7DR
Initial value : 0
R/W : R/W
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA
PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port A Register (PORTA)
Bit : 7
PA7
Initial value : —*
R/W : R
Note: * Determined by state of pins PA
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port
A pins (PA to PA ) must always be performed on PADR.
7 0
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed
while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and
PADR are initialized. PORTA retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port A MOS Pull-Up Control Register (PAPCR) (On-Chip ROM Version Only)
Bit : 7
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR
Initial value : 0
R/W : R/W
Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an
individual bit basis.
All the bits are valid in modes 6 and 7, and bits 7 to 5 are valid in modes 4 and 5. When a PADDR bit is cleared to 0
(input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
PAPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
6 5
PA6DR PA5DR PA4DR
0 0
R/W R/W R/W
6 5
PA6 PA5 PA4
—* —* —*
R R
to PA .
7 0
6 5
0 0
R/W R/W R/W
4 3 2
PA3DR PA2DR
0 0 0
R/W R/W
4 3 2
PA3 PA2
—* —*
R R R
4 3 2
0 0 0
R/W R/W
1 0
PA1DR PA0DR
0 0
R/W R/W
to PA ).
7 0
1 0
PA1 PA0
—* —*
R R
1 0
0 0
R/W R/W
Rev.6.00 Oct.28.2004 page 303 of 1016
REJ09B0138-0600H