Renesas H8S Series Hardware Manual page 741

ø
A to A
23 0
CS7 to CS0
AS
RD
(read)
D to D
15 0
(read)
HWR, LWR
(write)
D to D
15 0
(write)
WAIT
Figure 22-42 Basic Bus Timing (Three-State Access with One Wait State)
T T
1 2
t t
WTS WTH
T T
W 3
t t
WTS WTH
Rev.6.00 Oct.28.2004 page 713 of 1016
REJ09B0138-0600H