Samsung S3C6400X User Manual page 38

S3C6400
RISC MICROPROCESSOR
•
MISC
Signal I/O
XOM[4:0] I
XPWRRGTON O
XSELNAND I
XnBATF I
1.3.1.9 Power -supply Groups
•
VDD
Signal I/O
VDDALIVE
VDDARM
VDDINT
VDDMPLL
VDDAPLL
VDDEPLL
VDDOTG
VDDOTGI
VDDMMC
VDDHI
VDDLCD
VDDPCM
VDDEXT
VDDSYS
VDDUH
VDDADC
VDDDAC
VDDRTC
VDDM0
VDDM1
*Internal power for Core and cache @ 400Mhz is 1.0V
•
VSS
Signal
VSSIP
VSSMEM
VSSOTG
Operation mode selection. Refer System controller
Power Regulator enable
Select Flash Memory. 0 : OneNAND, 1 : NAND.
Battery fault indication
P Internal power for alive block
P Internal power for ARM1176 core and cache @ 533Mhz*
P Internal power for logic
P Power for MPLL core
P Power for APLL core
P Power for EPLL core
P Power for USB OTG PHY
P Internal power for USB OTG PHY
P IO power for SDMMC
P IO power for Host I/F
P IO power for LCD
P IO power for PCM ( Audio I/F – I2S, AC97)
P IO power for external I/F ( UART, I2C, Camera I/F, USB Host, etc.)
P IO power for system control. ( Clock, reset, operation mode, JTAG, etc)
P Power for USB Host
P Power for ADC core and IO
P Power for DAC core and IO
P Power for RTC logic and IO
P IO power for Memory Port 0
P IO power for Memory Port 1
I/O
G Internal Ground for Logic& ARM1176 core and cache
G IO ground for memory port 0 and 1
G Ground for USB OTG PHY.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
PRODUCT OVERVIEW
Voltage
1.0
1.1
1.0
1.0
1.0
1.0
3.3
1.0
1.8~3.3
1.8~3.3
1.8~3.3
1.8~3.3
1.8~3.3
1.8~3.3
3.3
3.3
3.3
2.5
1.8~2.85
1.8~2,5
1-35