Samsung S3C6400X User Manual page 29

PRODUCT OVERVIEW
XspiMOSI[0] IO IO
XspiCS[0] IO IO
XspiMISO[1] IO IO IO O
XspiCLK[1] IO IO O O
XspiMOSI[1] IO IO
XspiCS[1] IO IO
Signal I/O
XspiMISO[0] IO
XspiCLK[0] IO
XspiMOSI[0] IO
IO
XspiCS[0]
XspiMISO[1] IO
IO
XspiCLK[1]
XspiMOSI[1] IO
XspiCS[1] IO
ADDR_CF[2:0] O
EINT2[7:0] I
XmmcCMD2 IO
XmmcCLK2 O
•
PCM(2-Ch) / IIS / AC97
Signal
0 1 2 3 4
XpcmDCLK[0]
O IO I
XpcmEXTCLK[0]
I O O O
XpcmFSYNC[0]
O IO O O
XpcmSIN[0]
I I I
XpcmSOUT[0]
O O O
XpcmDCLK[1]
O IO I
XpcmEXTCLK[1]
I O O
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-26
O I GPC[2] XspiMOSI[0]
O I GPC[3]
I GPC[4] XspiMISO[1] XmmcCMD2
I GPC[5] XspiCLK[1]
O I GPC[6] XspiMOSI[1]
O I GPC[7]
SPI MISO[0]. SPI master data input line
SPI CLK[0]. SPI clock for channel 0
SPI MOSI[0]. SPI master data output line
SPI chip select(only for slave mode)
SPI MISO[1]. SPI master data input line
SPI CLK[1]. SPI clock for channel 1
SPI MOSI[1]. SPI master data output line
SPI chip select(only for slave mode)
CF card address
External Interrupt 2
COMMAND/RESPONSE (SD/SDIO/MMC card interface channel 2)
CLOCK (SD/SDIO/MMC card interface channel 2)
I/O
5 6 0
O IO I XpcmDCLK[0] Xi2sCLK[0]
IO I XpcmEXTCLK[0] Xi 2 sCDCLK[0]
IO I XpcmFSYNC[0]
XpcmSIN[0]
IO I
IO I XpcmSOUT[0]
IO I XpcmDCLK[1] Xi2sCLK[1]
IO I XpcmEXTCLK[1] Xi2sCDCLK[1] X97RESETn
XspiCS[0]
XmmcCLK2
XspiCS[1]
Description
Function
1 2
X97BITCLK
X97RESETn
Xi2sLRCK[0] X97SYNC
Xi2sDI[0] X97SDI
Xi2sDO[0] X97SDO
X97BITCLK
S3C6400 RISC MICROPROCESSOR
ADDR_CF[2]
3 4 5
ADDR_CF[0] GPD[0] EINT3[0]
ADDR_CF[1] GPD[1] EINT3[1]
ADDR_CF[2] GPD[2] EINT3[2]
GPD[3] EINT3[3]
GPD[4] EINT3[4]
GPE[0]
GPE[1]
]
EINT2[2
]
EINT2[3
]
EINT2[4
]
EINT2[5
]
EINT2[6
]
EINT2[7
]
6