Samsung S3C6400X User Manual page 27

PRODUCT OVERVIEW
Signal I/O
Xm1CKE[1:0] O
Xm1SCLK O
Xm1SCLKn O
Xm1CSn[1:0] O
Xm1ADDR[15:0] O
Xm1RASn O
Xm1CASn O
Xm1WEn O
Xm1DATA[15:0] IO
Xm1DATA[31:16] IO
Xm1DQM[3:0] O
Xm1DQS[3:0] IO
1.1.18.2 Serial Communication
•
UART / IrDA / CF
Signal
0 1 2 3 4
XuRXD[0]
I
XuTXD[0]
O
XuCTSn[0]
I
XuRTSn[0]
O
XuRXD[1]
I
XuTXD[1]
O
XuCTSn[1]
I
XuRTSn[1]
O
XuRXD[2]
I I I
XuTXD[2]
O O O O
XuRXD[3]
I I I
XuTXD[3]
O O O O
XirSDBW
O
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-24
Memory port 1 DRAM Clock Enable
Memory port 1 DRAM Clock
Memory port 1 DRAM Inverted Clock of Xm1SCLK
Memory port 1 DRAM Chip Select support up to 2 memory bank.
Memory port 1 DRAM Address bus
Memory port 1 DRAM Row Address Strobe
Memory port 1 DRAM Column Address Strobe
Memory port 1 DRAM Write Enable
Memory port 1 DRAM Lower Half Data bus.
Xm0ADDR[26:16] of SROMC.
Xm1DATA[31:16] can be used as Memory port 1 DRAM Upper Half Data bus by
System Controller setting.
Memory port 1 DRAM Data Mask
Memory port 1 DRAM Data Strobe
I/O
5 6 0
IO I XuRXD[0]
IO I XuTXD[0]
XuCTSn[0]
O IO I
XuRTSn[0]
O IO I
XuRXD[1]
IO I
XuTXD[1]
IO I
XuCTSn[1]
O IO I
XuRTSn[1]
O IO I
XuRXD[2]
O IO I
XuTXD[2]
IO I
XuRXD[3]
O IO I
IO I XuTXD[3]
IO I XirSDBW
Description
Function
1 2
ADDR_CF[0]
ADDR_CF[1]
ADDR_CF[0]
ADDR_CF[1]
XirRXD ADDR_CF[0]
XirTXD ADDR_CF[1]
XirRXD ADDR_CF[2]
XirTXD
S3C6400 RISC MICROPROCESSOR
3 4 5
GPA[0] EINT1[0]
GPA[1] EINT1[1]
GPA[2] EINT1[2]
GPA[3] EINT1[3]
GPA[4] EINT1[4]
GPA[5] EINT1[5]
GPA[6] EINT1[6]
GPA[7] EINT1[7]
GPB[0] EINT1[8]
GPB[1] EINT1[9]
GPB[2] EINT1[10]
GPB[3] EINT1[11]
GPB[4] EINT1[12]
6