Samsung S3C6400X User Manual page 26

S3C6400
RISC MICROPROCESSOR
RESET O
INPACK I
REG O
WEn O
OEn O
CDn I
DQM[1:0] O
RAS O
CAS O
SCLK O
SCLKn O
SCKE O
DQS[1:0] IO
WEn O
AP O
•
DRAM(mDDR and mSDRAM) Memory Port
•
Shared Memory Port (SROMC / DRAM1)
Signal
0
Xm1CKE
O
Xm1SCLK
IO
Xm1SCLKn
O
Xm1CSn[1:0]
O
Xm1ADDR[15:0]
O
Xm1RASn
O
Xm1CASn O
Xm1WEn
O
Xm1DATA[15:0]
IO
Xm1DATA[31:16]
IO
Xm1DQM[3:0]
O
Xm1DQS[3:0]
IO
Memory port 0 CF CARD Reset
Memory port 0 CF Input acknowledge in I/O mode
Memory port 0 CF Interrupt request from CF card
Memory port 0 CF Write enable strobe
Memory port 0 CF Output enable strobe
Memory port 0 CF Card detection
Memory port 0 DRAM Data Mask
Memory port 0 DRAM Row Address Strobe
Memory port 0 DRAM Column Address Strobe
Memory port 0 DRAM Clock
Memory port 0 DRAM Inverted Clock of Xm0SCLK
Memory port 0 DRAM Clock Enable
Memory port 0 DRAM Data Strobe
Memory port 0 DRAM Write Enable
Memory port 0 DRAM Auto Precharge
I/O
1
Xm1CKE
Xm1SCLK
Xm1SCLKn
Xm1CSN[1:0]
Xm1ADDR[15:0]
Xm1RAS
Xm1CAS
Xm1WEN
Xm1DATA[15:0]
Xm1DATA[31:16]
O
Xm1DQM[3:0]
Xm1DQS[3:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Function
0
PRODUCT OVERVIEW
1
Xm0ADDR[26:16]
1-23