Samsung S3C6400X User Manual page 41

MEMORY MAP
S3C6400X supports 32-bit physical address field and that address field can be seperated into two parts, one part
is for memory, the other part is for pheriperal.
Main memory is accessed via SPINE bus, and its address range is from 0x0000_0000 to 0x6FFF_FFFF. This
main memory part is seperated into four areas, boot image area, internal memory area, static memory area, and
dynamic memory area.
Address range of boot image area is from 0x0000_0000 to 0x07FF_FFFF, but there is no real mapped-memory.
Boot image area has mirrored image which points a partial region of internal memory area or static memory area.
Start address of boot image is fixed to 0x0000_0000.
Internal memory area is used to access internal ROM and internal SRAM for boot loader, which is also called
Steppingstone. Start address for each internal memory is fixed. Address range of internal ROM is from
0x0800_0000 to 0x0BFF_FFFF, but real storage is only 32KB. This region is read-only, and can be mapped to
boot image area when internal ROM booting is selected. Address range of internal SRAM is from 0x0C00_0000 to
0x0FFF_FFFF, but real storage is only 4KB. This region can be read and written, and can be mapped to boot
image area when NAND Flash booting is selected.
Address range of static memory area is from 0x1000_0000 to 0x3FFF_FFFF. SROM, SRAM, NOR Flash,
asyncronous NOR interface device, OneNAND Flash, and Steppingstone can be accessed by this address area.
Each area stands for a chip select, for example, address range from 0x1000_0000 to 0x17FF_FFFF stands for
Xm0CSn[0]. Start address for each chip select is fixed. NAND Flash and CF/ATAPI cannot be accessed via static
memory area, so if any of Xm0CSn[5:2] is mapped to NFCON or CFCON, related address region should not be
accessed. One exception is that if Xm0CSn[2] is used for NAND Flash, Steppingstone is mirrored to address
region from 0x2000_0000 to 27FF_FFFF.
Address range of dynamic memory area is from 0x4000_0000 to 0x6FFF_FFFF. DMC0 has right to use address
range from 0x4000_0000 to 0x4FFF_FFFF, and DMC1 has right to use address range from 0x5000_0000 to
0x6FFF_FFFF. Start address for each chip select is configurable.
Pheripheral is accessed via PERI bus, and its address range is from 0x7000_0000 to 0x7FFF_FFFF. All SFRs
can be accessed in this address range. Also, if data is needed to transfer from NFCON or CFCON, those data
should be transferred via PERI bus.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
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Specifications and information herein are subject to change without notice.
S3C6400X RISC MICROPROCESSOR