Ss Control Register 2 (Sscr2) - Renesas H8SX/1520 Series Hardware Manual

Bit Bit Name
0 CE
14.3.6

SS Control Register 2 (SSCR2)

SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS
pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of
the TEND bit.
Bit
Bit Name
Initial Value
R/W
Downloaded from Elcodis.com electronic components distributor
Initial
Value R/W
0 R/W
7 6
SDOS SSCKOS SCSOS
0 0
R/W R/W R/W
Section 14 Synchronous Serial Communication Unit (SSU)
Description
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave mode), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. Data reception does not
continue while the CE bit is set to 1. Serial transmission
also does not continue. Reset the SSU internal
sequencer by setting the SRES bit in SSCRL to 1
before resuming transfer after incomplete error.
[Setting condition]
When a low level is input to the SCS pin in master
•
mode (the MSS bit in SSCRH is set to 1)
When the SCS pin is changed to 1 during transfer in
•
slave mode (the MSS bit in SSCRH is cleared to 0)
[Clearing condition]
• When writing 0 after reading CE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
5 4 3
TENDSTS SCSATS
0 0 0
R/W R/W
2 1
SSODTS —
0 0
R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 521 of 804
REJ09B0104-0300
0
—
0
R/W