Operation In Asynchronous Communication - Renesas H8S/2100 Series Hardware Manual

17.4.2

Operation in Asynchronous Communication

Figure 17.2 illustrates the typical format for asynchronous serial communication. One frame
consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least
significant bit), a parity bit, and a stop bit (high level). In asynchronous serial communication, the
transmission line is usually held high in the mark state (high level). The SCIF monitors the
transmission line, and when it detects the space state (low level), recognizes a start bit and starts
serial communication. Inside the SCIF, the transmitter and receiver are independent units,
enabling full-duplex communication. Both of the transmitter and receiver also have a 16-stage
FIFO buffered structure so that data can be read or written during transmission or reception,
enabling continuous data transmission and reception.
1
Serial data
0
Start
bit
1 bit
Figure 17.2 Data Format in Serial Transmission/Reception
D0 D1 D2 D3
Transmit/receive data
5, 6, 7, or 8 bits
One unit of transfer data (character or frame)
(Example with 8-Bit Data, Parity and 2 Stop Bits)
Section 17 Serial Communication Interface with FIFO (SCIF)
D4 D5 D6 D7
Rev. 1.00 Apr. 28, 2008 Page 515 of 994
Idle state (mark state)
1
0/1
1 1
Parity Stop bit
bit
1 bit 1, 1.5,
or or
none 2 bits
REJ09B0452-0100