Reset Conditions; Interrupt Sources - Renesas H8S/2100 Series Hardware Manual

Section 16 CIR Interface
16.6

Reset Conditions

The range of initialization caused by a system reset, a software reset controlled by the SRES bit in
CCR1, or an abort is shown in table 16.6.
Table 16.6 Range of Initialization of CIR
HHMIN, HHMAX,
HLMIN, HLMAX,
DT0MIN, DT0MAX,
DT1MIN, DT1MAX,
CCR1, CCR2,
CEIR
System reset Initialized
SRES software Retained
reset
Abort Retained
16.7

Interrupt Sources

The CIR has six interrupt source flags for this LSI. Setting the corresponding enable bit to 1
enables the relevant interrupt request to be issued. Since the six interrupt requests are allocated to
one vector address, it is necessary for the CPU to check the interrupt request flags in order to
determine which interrupt source has caused the interrupt to be requested.
Table 16.7 Interrupt Sources
Interrupt Name
RENDI
OVEI
REPI
FREI
ABI
HEADFI
Rev. 1.00 Apr. 28, 2008 Page 490 of 994
REJ09B0452-0100
RFMBN bit
in HHMIN
Initialized
Initialized
Retained
Interrupt Source Flags
REND Receive end
OVRF Overrun error
REPF Repeat detection
FRF Framing error
ABF Abort
HEADF Header detection
CIRRDR CSTR
Initialized Initialized
Initialized Initialized
Retained Retained *
(CIRBUSY
is initialized.)
Sequence
Block
BRR
Initialized Initialized
Initialized Initialized
Initialized Retained
Interrupt Enable Bit
RENDIE
OVEIE
REPIE
FREIE
ABIE
HEADFIE