Reset Control - Renesas RZ Series User Manual

RZ Family / RZ/G, RZ/A Series
2.7

Reset Control

Figure 2.8 shows block diagrams of a reset control for the RTK9743U11S01000BE (Evaluation board Kit for
RZ/G2UL MPU).
For the RTK9743U11C01000BE, the interfaces of DDR4 SDRAM, QSPI flash memory, eMMC memory, Ethernet and
Debug are controlled by reset signal from the PMIC.
There are two types of system resets: power-on reset and reset by the button switch.
RESET_BTN#
5.0V
ISL80102
VIN
ENABLE
3.3V
ISL80102
VIN
ENABLE
5.0V
ISL61852
VIN
EN1
FLT1
EN2
FLT2
Note: shows the Carrier Board
Figure 2.8 Block Diagram of Reset Control
R01UH0990EJ0101 Rev.1.01
Jul 28, 2022
RESET_IN#
3.3V
VOUT
PG
1.8V
SLG7RN45356
VOUT
PG
5V_BOARD
OUT1
5V_PMOD
OUT2
RZ/G2UL SMARC Module Board
RZ/Five SMARC Module Board
RZ/G2UL
DDR_RESET#
QSPI_RESET#
SD0_RESET#
TRST#
PRST#
WDTOVF_PERROUT#
1.8V->3.3V
PRESET#_18
PMIC
NRESET
* You can use reset signal(TRST#) from JTAG.
If you want to use TRST# signal, please see the section2.9
2. Functional Specifications
RZ/A3UL SMARC Module Board
QSPI Edition
RZ/A3UL SMARC Module Board
OCTAL Edition
DDR4 SDRAM
RESET_N
QSPI flash memory
RESET#
eMMC memory
RST_#
Ethernet PHY_0
RESET_N
Ethernet PHY_1
RESET_N
JTAG conn
nRESET
GNDDetect(TRST#)
DNF*
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