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1
1.3.1 Processor Status Word Register: PSW (CR0)
b0
1
2
0
0
0
b16
17
18
BSM
BIE
?
?
0
b
Bit Name
0-15
No function assigned. Fix to "0".
16
BSM
Backup SM Bit
17
BIE
Backup IE Bit
18-22 No function assigned. Fix to "0".
23
BC
Backup C Bit
24
SM
Stack Mode Bit
25
IE
Interrupt Enable Bit
26-30 No function assigned. Fix to "0".
31
C
Condition Bit
The Processor Status Word Register (PSW) indicates the M32R-FPU status. It
consists of the current PSW field which is regularly used, and the BPSW field where
a copy of the PSW field is saved when EIT occurs.
The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and
the Condition (C) bit.
The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt
Enable (BIE) bit and the Backup Condition (BC) bit.
At reset release, BSM, BIE and BC are undefined. All other bits are "0".
3
4
5
6
7
0
0
0
0
0
19
20
21
22
23
BC
0
0
0
0
?
BPSW field
< At reset release: "B'0000 0000 0000 0000 ??00 000? 0000 0000 >
Function
Saves value of SM bit when EIT occurs
Saves value of IE bit when EIT occurs
Saves value of C bit when EIT occurs
0: Uses R15 as the interrupt stack pointer
1: Uses R15 as the user stack pointer
0: Does not accept interrupt
1: Accepts interrupt
Indicates carry, borrow and overflow resulting
from operations (instruction dependent)
CPU PROGRAMMING MODEL
8
9
10
11
0
0
0
0
24
25
26
27
SM
IE
0
0
0
0
PSW field
1-4
M32R-FPU Software Manual (Rev.1.01)
1.3 Control Registers
12
13
14
b15
0
0
0
0
28
29
30
b31
C
0
0
0
0
R
W
0
0
R
W
R
W
0
0
R
W
R
W
R
W
0
0
R
W
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