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VMTTYP1, VMTTYP0 (Output)
VMA27 to VMA0 (Output)
VMWRITE, VMBENZ3 to VMBENZ0,
VMCTYP2 to VMCTYP0, VMSIZE1,
VMSIZE0, VMSEQ2 to VMSEQ0,
VMSTZ, VMBSTR, VBDC (Output)
VDCSZ7 to VDCSZ0 (Output)
VBDO31 to VBDO0 (Output)
VMTTYP1, VMTTYP0 (Output)
VMA27 to VMA0 (Output)
VMWRITE, VMBENZ3 to VMBENZ0,
VMCTYP2 to VMCTYP0, VMSIZE1,
VMSIZE0, VMSEQ2 to VMSEQ0,
VMSTZ, VMBSTR, VBDC (Output)
VDCSZ7 to VDCSZ0 (Output)
VBDO31 to VBDO0 (Output)
Remark O mark: Sampling timing
:
Arbitrary input level
CHAPTER 4 BCU
Figure 4-17. Bus Master Transition Timing
Bus master
<1>
VBCLK (Input)
VAREQ (Input)
VAACK (Output)
VMLOCK (Output)
VDSELPZ (Output)
H
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
VMLOCK (Output)
VDSELPZ (Output)
H
D.0
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
Preliminary User's Manual A14874EJ3V0UM
M1
M2
<2>
<3> <4> <5> <6>
(1,0)
A.2
Ctrl.2
CS.2
D.2
(1,1)
(0,0)
A.1
Ctrl.1
CS.1
D.1
M1
A.3
Ctrl.3
CS.3
M2
M1
115
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