Transition Timing; Figure 6.56 Bus Released State Transition Timing - Renesas H8S/2368 Series Hardware Manual

6.10.3

Transition Timing

Figure 6.56 shows the timing for transition to the bus released state.
External space
access cycle
Address bus
Data bus
,
[1] Low level of
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of
[3] signal is driven low, releasing bus to external bus master.
[4] signal state is also sampled in external bus released state.
[5] High level of
[6] signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
bus release while BREQOE bit is set to 1,
[8] Normally
Note: However that if
kept low until a CBR refresh cycle starts.
T T
1 2
[1] [2] [3]
signal is sampled at rise of φ.
signal.
signal is sampled.
signal goes high 1.5 states after rising edge of
is asserted by a CBR refresh request,

Figure 6.56 Bus Released State Transition Timing

External bus released state
High-Z
High-Z
High-Z
High-Z
High-Z
[4] [5]
signal goes low.
signal.
signal is
Rev. 2.00, 05/03, page 193 of 820
[6] [7]
CPU
cycle
[8]