Figure 12.35 Deep Power-Down Mode Transition Timing - Renesas HD6417641 Hardware Manual

• Deep power-down mode
The low-power SDRAM supports the deep power-down mode as a low-power consumption
mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the
deep power-down mode, self-refresh will not be performed on any memory area. This mode is
effective in systems where all of the system memory areas are used as work areas.
If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to
1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0,
the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access
after returning from the deep power-down mode, the power-up sequence must be re-executed.
CKIO
CKE
A25 to A0
1
A12/A11*
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.

Figure 12.35 Deep Power-Down Mode Transition Timing

Tp Tpw Tdpd Trc
2. The waveform for DACKn is when active low is specified.
Section 12 Bus State Controller (BSC)
Trc Trc Trc Trc
Hi-Z
Rev. 4.00 Sep. 14, 2005 Page 375 of 982
REJ09B0023-0400