Transition Timing - Renesas H8S/2633 Series Hardware Manual

7.10.4

Transition Timing

Figure 7-39 shows the timing for transition to the bus-released state.
T
0
ø
Address bus
Data bus
CSn
AS
RD
HWR, LWR
BREQ
BACK
BREQO*
Low level of BREQ pin is sampled at rise of T
[1]
BACK pin is driven low at end of CPU read cycle, releasing bus to external
[2]
bus master.
BREQ pin state is still sampled in external bus released state.
[3]
High level of BREQ pin is sampled.
[4]
BACK pin is driven high, ending bus release cycle.
[5]
BREQO signal goes high 1.5 clocks after BACK signal goes high.
[6]
Note: * Output only when BREQOE is set to 1.
236
CPU cycle
T T
1 2
Address
Minimum
1 state
[1]
2
Figure 7-39 Bus-Released State Transition Timing
External bus released state
[2] [3]
state.
CPU
cycle
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[4] [5] [6]