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Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from
E.1
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. The minimum delay
from the fall of the STBY signal to the rise of the RES signal is 0 ns.
STBY
RES
Figure E.1 Timing of Recovery from Hardware Standby Mode (1)
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents
do not need to be retained, RES does not have to be driven low as in (1).
E.2
Timing of Recovery from Hardware Standby Mode
Drive the RES signal low approximately 100 ns before STBY goes high.
STBY
RES
Figure E.2 Timing of Recovery from Hardware Standby Mode (2)
Hardware Standby Mode
≥ 10t
t
1
cyc
t ≥ 100 ns
≥
t
0 ns
2
t
OSC
Rev. 3.00 Mar 21, 2006 page 807 of 814
REJ09B0302-0300
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