Figure 20.2 Medium-Speed Mode Transition And Clearance Timing - Renesas H8S Series Hardware Manual

Section 20 Power-Down Modes
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 20.2 shows the timing for transition to and clearance of medium-speed mode.
φ,
supporting module clock
Bus master clock
Internal address bus
Internal write signal

Figure 20.2 Medium-Speed Mode Transition and Clearance Timing

Rev. 6.00 Mar 15, 2006 page 498 of 570
REJ09B0211-0600
SCKCR
Medium-speed mode
SCKCR