Transition Timing - Renesas H8S/2319 series Hardware Manual

6.7.4

Transition Timing

Figure 6-19 shows the timing for transition to the bus released state.
T
0
φ
Address bus
Data bus
AS
RD
HWR, LWR
BREQ
BACK
BREQO *
Low level of BREQ pin is sampled at rise of T
[1]
BACK pin is driven low at end of CPU read cycle, releasing bus to external
[2]
bus master.
BREQ pin state is still sampled in external bus released state.
[3]
High level of BREQ pin is sampled.
[4]
BACK pin is driven high, ending bus release cycle.
[5]
BREQO signal goes high 1.5 clocks after BACK signal goes high.
[6]
Note: * Output only when BREQOE is set to 1.
CPU cycle
T T
1 2
Address
Minimum
1 state
[1] [2]
Figure 6-19 Bus Released State Transition Timing
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
[3]
state.
2
Rev. 5.00, 12/03, page 179 of 1088
CPU
cycle
[4] [5] [6]