Chapter 3 Registers; Registers - Renesas EMMA Mobile 1 User Manual

Multimedia processor for mobile applications uart interface

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Table of Contents

UART register addresses use half-word boundaries.

3.1 Registers

The offset addresses 0000H to 0034H are assigned to UART registers, and 0040H to 0050H are assigned to IR

encoder/decoder registers.

Do not access reserved registers. The value 0000_0000H is returned for a read access.

Do not write any value other than 0 to the reserved bits in each register.

Base addresses: 5000_0000H (UART0), 5001_0000H (UART1), 5002_0000H (UART2)

Address

0000H

Receive buffer register

Transmit hold register

0004H

Interrupt enable register

0008H

Interrupt identification register

000CH

FIFO control register

0010H

Line control register

0014H

Modem control register

0018H

Line status register

001CH

Modem status register

0020H

Scratch register

0024H

Divisor latch LS byte register

0028H

Divisor latch MS byte register

002CH

Hardware control register

0030H

Hardware status register 2

0034H

Hardware status register 3

0038H

Reserved

003CH

Reserved

0040H

IR control register 0

0044H

IR control register 1

0048H

IR control register 2

004CH

IR control register 3

0050H

IR control register 4

Notes 1. Differs depending on the condition of the connected device.

2. Bit 7 (DLAB) of the LCR register must be set to 1 before setting up the DLL and DLM registers. The DLAB

bit must be set to 0 after writing to the DLL and DLM registers. For details, see 3.2.5 Line control