Example Of Setting X1 Oscillation Clock - Renesas RL78 Series User Manual

RL78/G1D

6.6.2 Example of setting X1 oscillation clock

After a reset release, the CPU/peripheral hardware clock (f
oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the oscillation stabilization time select register (OSTS) and clock operation mode control register (CMC) and clock
operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter
status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to f
register (CKC).
[Register settings] Set the register in the order of <1> to <5> below.
<1> Set (1) the OSCSEL bit of the CMC register, except for the cases where f
AMPH bit, to operate the X1 oscillator.
7
EXCLK
CMC
0
<2> Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode.
Example: Setting values when a wait of at least 102 µs is set based on a 10 MHz resonator.
7
OSTS
0
<3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
7
MSTOP
CSC
0
<4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
Example: Wait until the bits reach the following values when a wait of at least 102 µs is set based on a 10 MHz
resonator.
7
MOST8
OSTC
1
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
7
CLS
CKC
0
Caution Keep the operating voltage within the range that allows operation of the flash memory as set in an
option byte (000C2H) before and after changes to the main system clock (f
clock control register (CKC).
Option Byte (000C2H) Value
CMODE1 CMODE0
0 0
1 0
1 1
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
6 5
OSCSEL EXCLKS OSCSELS
1 0
6 5
0 0
6 5
XTSTOP
1 0
6 5
MOST9 MOST10
1 1
6 5
CSS MCS
0 0
Flash Operation Mode
LV (low-voltage main) mode
LS (low-speed main) mode
HS (high-speed main) mode
CHAPTER 6 CLOCK GENERATOR
) always starts operating with the high-speed on-chip
CLK
4 3
AMPHS1
0 0
4 3
OSTS2
0 0
4 3
0 0
4 3
MOST11 MOST13 MOST15
0 0
4 3
MCM0
1 0
Operating Frequency Range
1 MHz to 4 MHz
1 MHz to 8 MHz
1 MHz to 16 MHz
1 MHz to 32 MHz
by using the system clock control
CLK
> 10 MHz, in such cases set (1) the
X
2 1 0
AMPHS0 AMPH
0 0 0/1
2 1 0
OSTS1 OSTS0
0 1 0
2 1 0
HIOSTOP
0 0 0
2 1 0
MOST17 MOST18
0 0 0
2 1 0
0 0 0
) by using the system
MAIN
Operating Voltage Range
1.6 V to 3.6 V
1.8 V to 3.6 V
2.4 V to 3.6 V
2.7 V to 3.6 V
139