Renesas RL78 Series User Manual page 80

RL78/G1D
Notes 1. The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to
1 after reset.
2. The reset values of the registers vary depending on the reset source as shown below.
Reset Source RESET Input
Register
RESF TRAP bit Cleared (0)
WDTRF bit
RPERF bit
IAWRF bit
LVIRF bit
LVIM LVISEN bit Cleared (0)
LVIOMSK bit Held
LVIF bit
LVIS
3. The reset value of the WDTE register is determined by the setting of the option byte.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Reset by Reset by
POR Execution of
Illegal
Instruction
Set (1)
Held
Held
Held
Held
Cleared (00H/01H/81H)
CHAPTER 4 CPU ARCHITECTURE
Reset by Reset by
WDT RAM parity
error
Held
Set (1) Held
Set (1)
Reset by Reset by
illegal- LVD
memory
access
Held
Held
Set (1)
Set (1)
Held
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