Renesas RL78 Series User Manual page 550

RL78/G1D
Note 1
SPIEn
0 Disable
1 Enable
If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn
= 1.
Condition for clearing (SPIEn = 0)
● Cleared by instruction
● Reset
Note 1
WTIMn
0 Interrupt request is generated at the eighth clock's falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1 Interrupt request is generated at the ninth clock's falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of
this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is
inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local
address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However,
when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIMn = 0)
● Cleared by instruction
● Reset
Notes 1,
ACKEn
2
0 Disable acknowledgment.
1 Enable acknowledgment. During the ninth clock period, the SDAAn line is set to low level.
Condition for clearing (ACKEn = 0)
● Cleared by instruction
● Reset
Notes 1. The signal of this bit is invalid while IICEn is 0. Set this bit during that period.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated
regardless of the set value.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-6. Format of IICA Control Register n0 (IICCTLn0) (2/4)
Enable/disable generation of interrupt request when stop condition is detected
Control of wait and interrupt request generation
CHAPTER 14 SERIAL INTERFACE IICA
Condition for setting (SPIEn = 1)
● Set by instruction
Condition for setting (WTIMn = 1)
● Set by instruction
Acknowledgment control
Condition for setting (ACKEn = 1)
● Set by instruction
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