Renesas RL78 Series User Manual page 856

RL78/G1D
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, supporting
CSI00 only)
(T = –40 to +85°C, 2.7 V ≤ V
A
Parameter
SCKp cycle time
SCKp high-/low-level
width
SIp setup time (to SCKp↑)
Note 1
SIp hold time (from SCKp↑
Note 1
Delay time from SCKp↓ to
Note 2
SOp output
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp time becomes "to SCKp↓"
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
"from SCKp↑" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. C is the load capacitance of the SCKp and SOp output lines.
Cautions Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. This specification is valid only when CSI00's peripheral I/O redirect function is not used.
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
3. f : Serial array unit operation clock frequency
MCK
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (mn = 00))
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
= V = AV
DD DD_RF DD_RF
Symbol Conditions
t t ≥ 2/f
KCY1 KCY1 CLK
t ,
KH1
t
KL1
t
SIK1
t
KSI1
Note 3
t C = 20 pF
KSO1
CHAPTER 30 ELECTRICAL SPECIFICATIONS
≤ 3.6 V, V = V = AV
SS SS_RF
HS (high-speed
main) Mode
MIN.
83.3
t /2 –
KCY1
10
33
10
= 0 V)
SS_RF
LS (low-speed LV (low-voltage
main) Mode main) Mode
MAX. MIN. MAX. MIN.
250 500
t /2 – t
KCY1 KCY1
50 50
110 110
10 10
10 10
Unit
MAX.
ns
/2 – ns
ns
ns
10 ns
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