Renesas RL78 Series User Manual page 406

RL78/G1D
13.3.6 Serial flag clear trigger register mn (SIRmn)
The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared
immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 13-10. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03),
F0148H, F0149H (SIR10), F014AH, F014BH (SIR11)
Symbol 15 14
SIRmn 0 0
Note
FECTmn
0
1
PECTmn
0
1
OVCTmn
0
1
Note The SIR01 and SIR03 registers only.
Caution Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR00, SIR02, SIR10, or SIR11 register) to "0".
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3 for m = 0, n = 0, 1 for m = 1)
2. When the SIRmn register is read, 0000H is always read.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
13 12 11 10
0 0 0 0
Not cleared
Clears the FEFmn bit of the SSRmn register to 0.
Not cleared
Clears the PEFmn bit of the SSRmn register to 0.
Clear trigger of overrun error flag of channel n
Not cleared
Clears the OVFmn bit of the SSRmn register to 0.
After reset: 0000H
9 8 7 6
0 0 0 0
Clear trigger of framing error of channel n
Clear trigger of parity error flag of channel n
CHAPTER 13 SERIAL ARRAY UNIT
R/W
5 4 3 2
0 0 0 FECT
Note
mn
1 0
PEC OVC
Tmn Tmn
385