Renesas RL78 Series User Manual page 432

RL78/G1D
13.5.2 Master reception
Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from other device.
3-Wire Serial I/O
Target channel
Pins used
Note 1
Interrupt
Note 1
Error detection flag
Note 1
Transfer data length
Notes 1, 2
Transfer rate
Note 1
Data phase
Note 1
Clock phase
Note 1
Data direction
Notes 1. CSI21 cannot be used for master reception.
2. Use this operation within a range that satisfies the conditions above and the peripheral functions
characteristics in the electrical specifications (see CHAPTER 30 ELECTRICAL SPECIFICATIONS).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0), mn = 00, 10
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CSI00
Channel 0 of SAU0
SCK00, SI00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Overrun error detection flag (OVFmn) only
7 or 8 bits
Max. f /2 [Hz] (CSI00 only), f
CLK
15
Min. f /(2 × 2 × 128) [Hz]
CLK
Selectable by the DAPmn bit of the SCRmn register
● DAPmn = 0: Data input starts from the start of the operation of the serial clock.
● DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Selectable by the CKPmn bit of the SCRmn register
● CKPmn = 0: Non-reverse
● CKPmn = 1: Reverse
MSB or LSB first
CHAPTER 13 SERIAL ARRAY UNIT
CSI20
Channel 0 of SAU1
SCK20, SI20
INTCSI20
/4 [Hz]
CLK
f : System clock frequency
CLK
CSI21
Channel 1 of SAU1
–
–
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