Renesas RL78 Series User Manual page 506

RL78/G1D
13.6.3 SNOOZE mode function
The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP
mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the
UART to perform reception operations without CPU operation.
Only UART0 can be set to the SNOOZE mode.
When using UART0 in the SNOOZE mode, make the following settings before entering the STOP mode. (See Figure
13-71 and Figure 13-73 Flowchart of SNOOZE Mode Operation.)
● In the SNOOZE mode, the baud rate setting for UART reception needs to be changed to a value different from that in
normal operation. Set the SPSm register and bits 15 to 9 of the SDRmn register with reference to Table 13-3.
● Set the EOCmn and SSECmn bits. This is for enabling or stopping generation of an error interrupt (INTSRE0) when a
communication error occurs.
● When using the SNOOZE mode function, set the SWCm bit of serial standby control register m (SSCm) to 1 just before
switching to the STOP mode. After the initial setting has completed, set the SSm1 bit of serial channel start register m
(SSm) to 1.
● A UARTq starts reception in SNOOZE mode on detecting input of the start bit on the RxDq pin following a transition of
the CPU to the STOP mode.
Cautions 1. The SNOOZE mode can only be used when the high-speed on-chip oscillator clock (f
for f .
CLK
2. The transfer rate in the SNOOZE mode is only 4800 bps.
3. When SWCm = 1, UARTq can be used only when the reception operation is started in the STOP
mode.
reception operation is started in a state other than the STOP mode, such as those given below,
data may not be received correctly and a framing error or parity error may be generated.
● When after the SWCm bit has been set to 1, the reception operation is started before the STOP
mode is entered
● When the reception operation is started while another function is in the SNOOZE mode
● When after returning from the STOP mode to normal operation due to an interrupt or other
cause, the reception operation is started before the SWCm bit is returned to 0
4. If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFmn,
FEFmn, or OVFmn flag is not set and an error interrupt (INTSREq) is not generated. Therefore,
when the setting of SSECm = 1 is made, clear the PEFmn, FEFmn, or OVFmn flag before setting
the SWC0 bit to 1 and read the value in bits 7 to 0 (RxDq register) of the SDRm1 register.
5. The CPU shifts from the STOP mode to the SNOOZE mode on detecting the valid edge of the RxDq
signal. Note, however, that transfer through the UART channel may not start and the CPU may
remain in the SNOOZE mode if an input pulse on the RxDq pin is too short to be detected as a
start bit.
In such cases, data may not be received correctly, and this may lead to a framing error or parity
error in the next UART transfer.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
When used simultaneously with another SNOOZE mode function or interrupt, if the
CHAPTER 13 SERIAL ARRAY UNIT
) is selected
IH
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