Renesas RL78 Series User Manual page 817

RL78/G1D
29.2 Operation List
Instruction Mnemonic
Group
8-bit data MOV r, #byte
transfer
PSW, #byte
CS, #byte
ES, #byte
!addr16, #byte
ES:!addr16, #byte
saddr, #byte
sfr, #byte
[DE+byte], #byte
ES:[DE+byte],#byte
[HL+byte], #byte
ES:[HL+byte],#byte
[SP+byte], #byte
word[B], #byte
ES:word[B], #byte
word[C], #byte
ES:word[C], #byte
word[BC], #byte
ES:word[BC], #byte
A, r
r, A
A, PSW
PSW, A
A, CS
CS, A
A, ES
ES, A
A, !addr16
A, ES:!addr16
!addr16, A
ES:!addr16, A
A, saddr
saddr, A
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
accessed by an 8-bit instruction.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 29-5. Operation List (1/17)
Operands Bytes
Note 1 Note 2
2
3
3
2
4
5
3
3
3
4
3
4
3
4
5
4
5
4
5
Note 3
1
Note 3
1
2
2
2
2
2
2
3
4
3
4
2
2
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the code flash memory is accessed, or when the data flash memory is
CLK
Clocks
1 – r ← byte
3 – PSW ← byte
1 – CS ← byte
1 – ES ← byte
1 – (addr16) ← byte
2 – (ES, addr16) ← byte
1 – (saddr) ← byte
1 – sfr ← byte
1 – (DE+byte) ← byte
2 – ((ES, DE)+byte) ← byte
1 – (HL+byte) ← byte
2 – ((ES, HL)+byte) ← byte
1 – (SP+byte) ← byte
1 – (B+word) ← byte
2 – ((ES, B)+word) ← byte
1 – (C+word) ← byte
2 – ((ES, C)+word) ← byte
1 – (BC+word) ← byte
2 – ((ES, BC)+word) ← byte
1 – A ← r
1 – r ← A
1 – A ← PSW
3 – PSW ← A
1 – A ← CS
1 – CS ← A
1 – A ← ES
1 – ES ← A
1 4 A ← (addr16)
2 5 A ← (ES, addr16)
1 – (addr16) ← A
2 – (ES, addr16) ← A
1 – A ← (saddr)
1 – (saddr) ← A
CHAPTER 29 INSTRUCTION SET
Operation Flag
Z AC CY
× × ×
× × ×
796