Renesas RL78 Series User Manual page 281

RL78/G1D
Figure 7-78. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
TAU
default
setting
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel Sets timer mode registers mn, mp, 0q (TMRmn, TMRmp,
default TMRmq) of each channel to be used (determines
setting operation mode of channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp and TDRmq registers of the slave
channels.
Sets slave channels.
The TOM0p and TOM0q bits of timer output mode
register m (TOM0) are set to 1 (slave channel output
mode).
Sets the TOL0p and TOL0q bits.
Sets the TO0p and TO0q bits and determines default
level of the TO0p and TO0q outputs.
Sets the TOE0p and TOE0q bits to 1 and enables
operation of TO0p and TO0q.
Clears the port register and port mode register to 0.
(Remark is listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO0p and TO0q pins go into Hi-Z output state.
The TO0p and TO0q default setting levels are output when
the port mode register is in output mode and the port
register is 0.
TO0p and TO0q do not change because channels stop
operating.
The TO0p and TO0q pins output the TO0p and TO0q set
levels.
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