Renesas RL78 Series User Manual page 478

RL78/G1D
Figure 13-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Write 1 to MDmn0 bit
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 13-68
Transmission/Reception (in Continuous Transmission/Reception Mode).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Starting setting
<1>
SAU default setting
Setting
transmission/reception data
Enables interrupt
Wait for transmission completes
<3> <6>
Buffer empty/transfer end interrupt
BFFmn = 1?
Yes
Read receive data to SIOp
<4>
(=SDRmn[7:0])
<7>
Subtract -1 from number of
transmit data
= 0
Number of communication
data?
Yes
≥ 2
Writing transmit data to
SIOp (=SDRmn[7:0])
RETI
No
Number of communication
data = 0?
Yes
Yes
Communication
continued?
No
Disable interrupt (MASK)
<8>
Write 1 to STmn bit
End of communication
CHAPTER 13 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 13-62
(Select buffer empty interrupt)
Setting storage area and number of data for transmission/reception data
(Storage area, Transmission/reception data pointer, Number of communication data
and Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Start communication when master start providing the
clock
When buffer empty/transfer end is generated, it moves
interrupt processing routine
No
Other than the first interrupt, read reception data then writes
to storage area, update receive data pointer
If transmit data is remained (number of communication data ≥ 2),
= 1
read it from storage area, write it to SIOp, and then, update
storage pointer.
If transmit is completed (number of communication data = 1),
change to transfer end interrupt.
<5>
Clear MDmn0 bit to 0
Timing Chart of Slave
457