Renesas RL78 Series User Manual page 866

RL78/G1D
Maximum transfer rate = 1/{-Cb × Rb × ln (1 - 1.5/Vb)} × 3 [bps]
Baud rate error (theoretical value) =
(1/transfer rate × 2 - {-Cb × Rb × ln (1 - 1.5/Vb)} / (1/transfer rate) × number of transferred bits)
Note 7. This value as an example is calculated when the conditions described in the "Conditions" column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V
TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V
and V , see the DC characteristics with TTL input buffer selected.
IL
Remarks 1. R [Ω]:Communication line (TxDq) pull-up resistance,
b
C [F]: Communication line (TxDq) load capacitance, V
b
2. q: UART number (q = 0, 1), g: PIM and POM numbers (g = 0, 1)
3. f : Serial array unit operation clock frequency
MCK
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03))
UART mode connection diagram (during communication at different potential)
UART mode bit width (during communication at different potential) (reference)
TxDq
RxDq
Remarks 1. R [Ω]:Communication line (TxDq) pull-up resistance, V
b
2. q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
TxDq
RL78 microcontroller
RxDq
Baud rate error tolerance
CHAPTER 30 ELECTRICAL SPECIFICATIONS
[V]: Communication line voltage
b
V
b
R
b
Rx
User device
Tx
1/Transfer rate
1/Transfer rate
High-/Low-bit width
[V]: Communication line voltage
b
tolerance) mode for the
DD
Low-bit width
High-bit width
Baud rate error tolerance
IH
845