Renesas RL78 Series User Manual page 468

16-bit single-chip microcontrollers
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RL78/G1D
Figure 13-61. Flowchart of Slave Reception (in Single-Reception Mode)
No
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Starting CSI communication
SAU default setting
Ready for reception
Enables interrupt
Wait for receive completes
Transfer end interrupt
Reading receive data to
SIOp (=SDRmn[7:0])
RETI
Reception completed?
Yes
Disable interrupt (MASK)
Write STmn bit to 1
Clear SAUmEN bit of the
PER0 register to 0
End of communication
CHAPTER 13 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 13-57.
(Select transfer end interrupt only)
Clear storage area setting and the number of receive data
(Storage area, Reception data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI).
Start communication when master start providing
the clock
When transmit end, interrupt is generated
Read receive data then writes to storage area, and counts
up the number of receive data.
Update receive data pointer.
Check completion of number of receive data
447

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