Renesas RL78 Series User Manual page 496

RL78/G1D
Figure 13-80. Flowchart of UART Transmission (in Single-Transmission Mode)
Starting UART communication
Writing transmit data to
(TXDq register) (8 bits) or
the SDRmn[8:0] bits (9 bits)
Wait for transmit completes
Writing transmit data to the
(TXDq register) (8 bits) or
the SDRmn[8:0] bits (9 bits)
No
Disable interrupt (MASK)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
SAU default setting
Setting transmit data
Enables interrupt
the SDRmn[7:0] bits
Transfer end interrupt
Transmitting next data?
Yes
SDRmn[7:0] bits
RETI
Transmission completed?
Yes
Write 1 to STmn bit
End of communication
For the initial setting, refer to Figure 13-75.
(Select transfer end interrupt)
Set data for transmission and the number of data. Clear communication end flag
(Storage area, transmission data pointer, number of communication data and
communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI).
Read transmit data from storage area and write it
to TxDq. Update transmit data pointer.
Read transmit data, if any, from storage area and
No
write it to TxDq. Update transmit data pointer.
If not, set transmit end flag
Sets communication
completion flag
Check completion of transmission by
verifying transmit end flag
CHAPTER 13 SERIAL ARRAY UNIT
Transmission starts by writing
to the SDRmn[7:0] bits.
When Transfer end interrupt is generated, it
moves to interrupt processing routine
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