Renesas RL78 Series User Manual page 827

RL78/G1D
Instruction
Mnemonic
Group
16-bit ADDW AX, #word
operation
AX, AX
AX, BC
AX, DE
AX, HL
AX, !addr16
AX, ES:!addr16
AX, saddrp
AX, [HL+byte]
AX, ES: [HL+byte]
SUBW AX, #word
AX, BC
AX, DE
AX, HL
AX, !addr16
AX, ES:!addr16
AX, saddrp
AX, [HL+byte]
AX, ES: [HL+byte]
CMPW AX, #word
AX, BC
AX, DE
AX, HL
AX, !addr16
AX, ES:!addr16
AX, saddrp
AX, [HL+byte]
AX, ES: [HL+byte]
Multiply MULU X
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 29-5. Operation List (11/17)
Operands Bytes
Note 1 Note 2
3
1
1
1
1
3
4
2
3
4
3
1
1
1
3
4
2
3
4
3
1
1
1
3
4
2
3
4
1
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the code flash memory is accessed, or when the data flash memory is
CLK
Clocks
1 – AX, CY ← AX+word
1 – AX, CY ← AX+AX
1 – AX, CY ← AX+BC
1 – AX, CY ← AX+DE
1 – AX, CY ← AX+HL
1 4 AX, CY ← AX+(addr16)
2 5 AX, CY ← AX+(ES:addr16)
1 – AX, CY ← AX+(saddrp)
1 4 AX, CY ← AX+(HL+byte)
2 5 AX, CY ← AX+((ES:HL)+byte)
1 – AX, CY ← AX – word
1 – AX, CY ← AX – BC
1 – AX, CY ← AX – DE
1 – AX, CY ← AX – HL
1 4 AX, CY ← AX – (addr16)
2 5 AX, CY ← AX – (ES:addr16)
1 – AX, CY ← AX – (saddrp)
1 4 AX, CY ← AX – (HL+byte)
2 5 AX, CY ← AX – ((ES:HL)+byte)
1 – AX – word
1 – AX – BC
1 – AX – DE
1 – AX – HL
1 4 AX – (addr16)
2 5 AX – (ES:addr16)
1 – AX – (saddrp)
1 4 AX – (HL+byte)
2 5 AX – ((ES:HL)+byte)
1 – AX ← A×X
CHAPTER 29 INSTRUCTION SET
Operation Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
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