Renesas RL78 Series User Manual page 705

16-bit single-chip microcontrollers
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RL78/G1D
Table 18-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
Multiple Interrupt Request
Interrupt Being Serviced
Maskable interrupt
ISP1 = 0
ISP0 = 0
ISP1 = 0
ISP0 = 1
ISP1 = 1
ISP0 = 0
ISP1 = 1
ISP0 = 1
Software interrupt
Remarks 1.
: Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. ISP0, ISP1, and IE are flags contained in the PSW.
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced.
ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced.
ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced.
ISP1 = 1, ISP0 = 1: Wait for an interrupt acknowledgment (all interrupts are enabled).
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
4. PR is a flag contained in the PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, and PR12H registers.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
During Interrupt Servicing
Maskable Interrupt Request
Priority Level 0
Priority Level 1
(PR = 00)
(PR = 01)
IE = 1
IE = 0
IE = 1
×
×
×
×
×
×
CHAPTER 18 INTERRUPT FUNCTIONS
Priority Level 2
(PR = 10)
IE = 0
IE = 1
IE = 0
×
×
×
×
×
×
×
×
×
×
×
×
Software
Interrupt
Priority Level 3
Request
(PR = 11)
IE = 1
IE = 0
×
×
×
×
×
×
×
×
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