Renesas RL78 Series User Manual page 227

RL78/G1D
(3) Operation of TO0n pin in slave channel output mode (TOM0n = 1)
(a) When timer output level register 0 (TOL0) setting has been changed during timer operation
When the TOL0 register setting has been changed during timer operation, the setting becomes valid at the
generation timing of the TO0n pin change condition. Rewriting the TOL0 register does not change the output
level of the TO0n pin.
The operation when TOM0n is set to 1 and the value of the TOL0 register is changed while the timer is
operating (TE0n = 1) is shown below.
Figure 7-33. Operation when TOL0 Register Has Been Changed Contents during Timer Operation
TOL0
TO0n
(output)
Remarks 1. Set:
Reset:
2. n: Channel number (n = 0 to 7)
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 7-34 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel:
Slave channel:
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Active
Reset
Set Set
The output signal of the TO0n pin changes from inactive level to active level.
The output signal of the TO0n pin changes from active level to inactive level.
TOEmn = 1, TOMmn = 0, TOLmn = 0
TOEmp = 1, TOMmp = 1, TOLmp = 0
Active Active
Reset
Set
CHAPTER 7 TIMER ARRAY UNIT
Active
Reset Reset
Set
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