Renesas RL78 Series User Manual page 517

16-bit single-chip microcontrollers
Hide thumbs Also See for RL78 Series:
Table of Contents

Advertisement

RL78/G1D
(3) Permissible baud rate range for reception
The permissible baud rate range for reception during UART (UART0 and UART1) communication can be
calculated by the following expression. Make sure that the baud rate at the transmission side is within the
permissible baud rate range at the reception side.
(Maximum receivable baud rate) =
(Minimum receivable baud rate) =
Brate: Calculated baud rate value at the reception side (See 13.6.4 (1) Baud rate calculation expression.)
k:
SDRmn[15:9] + 1
Nfr:
1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
Remark m: Unit number (m = 0), n: Channel number (n = 1, 3), mn = 01, 03
Figure 13-94. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
Data frame length
of SAU
Permissible minimum
data frame length
Permissible maximum
data frame length
As shown in Figure 13-94, the timing of latching receive data is determined by the division ratio set by bits 15 to 9
of serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this
latch timing, the data can be correctly received.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
2 × k × Nfr
2 × k × Nfr – k + 2
2 × k × (Nfr – 1)
2 × k × Nfr – k – 2
Latch
timing
Start
Bit 0
Bit 1
bit
FL
Start
Bit 0
Bit 1
bit
Start
Bit 0
Bit 1
bit
CHAPTER 13 SERIAL ARRAY UNIT
× Brate
× Brate
Parity
Bit 7
1 data frame (11 ´ FL)
Parity
Bit 7
bit
(11 ´ FL) min.
Bit 7
(11 ´ FL) max.
Stop
bit
bit
Stop
bit
Parity
Stop
bit
bit
496

Advertisement

Table of Contents
loading

This manual is also suitable for:

Rl78/g1dR5f11aggR5f11aghR5f11agj

Table of Contents