Renesas RL78 Series User Manual page 435

RL78/G1D
(2) Operation procedure
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Writing to the SSm register
(Selective)
(Essential)
(Essential)
(Selective)
(Selective)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-33. Initial Setting Procedure for Master Reception
Starting initial setting
Setting the SOm register
Setting port
End of initial setting
Figure 13-34. Procedure for Stopping Master Reception
Starting setting to stop
TSFmn = 0?
Yes
Writing the STm register
Changing setting of the SOEm register
Changing setting of the SOm register
Setting the PER0 register
Stop setting is completed
CHAPTER 13 SERIAL ARRAY UNIT
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (f )).
MCK
Set the initial output level of the serial
clock (CKOmn).
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1: to enable operation).
Set dummy data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
If there is any data being transferred, wait for
No
their completion.
(If there is an urgent must stop, do not wait)
Write 1 to the STmn bit of the target channel.
(SEmn = 0: to operation stop status)
Set the SOEmn bit to 0 and stop the output of
the target channel.
The levels of the serial clock (CKOmn) and
serial data (SOmn) on the target channel can
be changed if necessitated by an emergency.
Reset the serial array unit by stopping the
clock supply to it.
The master transmission is stopped.
Go to the next processing.
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