Renesas RL78 Series User Manual page 820

RL78/G1D
Instruction
Mnemonic
Group
8-bit data XCH A, [HL+B]
transfer
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
ONEB A
X
B
C
!addr16
ES:!addr16
saddr
CLRB A
B
C
!addr16
ES:!addr16
saddr
MOVS [HL+byte], X
ES:[HL+byte], X
16-bit MOVW rp, #word
data
saddrp, #word
transfer
sfrp, #word
AX, rp
rp, AX
AX, !addr16
!addr16, AX
AX, ES:!addr16
ES:!addr16, AX
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
accessed by an 8-bit instruction.
3. Except rp = AX
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 29-5. Operation List (4/17)
Operands Bytes
Note 1 Note 2
2
3
2
3
1
1
1
1
3
4
2
1
1
1
3
4
2
3
4
3
4
4
Note 3
1
Note 3
1
3
3
4
4
2
2
2
2
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the code flash memory is accessed, or when the data flash memory is
CLK
Clocks
2 – A ←→ (HL+B)
3 – A ←→ ((ES, HL)+B)
2 – A ←→ (HL+C)
3 – A ←→ ((ES, HL)+C)
1 – A ← 01H
1 – X ← 01H
1 – B ← 01H
1 – C ← 01H
1 – (addr16) ← 01H
2 – (ES, addr16) ← 01H
1 – (saddr) ← 01H
1 – A ← 00H
1 – B ← 00H
1 – C ← 00H
1 – (addr16) ← 00H
2 – (ES,addr16) ← 00H
1 – (saddr) ← 00H
1 – (HL+byte) ← X
2 – (ES, HL+byte) ← X
1 – rp ← word
1 – (saddrp) ← word
1 – sfrp ← word
1 – AX ← rp
1 – rp ← AX
1 4 AX ← (addr16)
1 – (addr16) ← AX
2 5 AX ← (ES, addr16)
2 – (ES, addr16) ← AX
1 – AX ← (saddrp)
1 – (saddrp) ← AX
1 – AX ← sfrp
1 – sfrp ← AX
CHAPTER 29 INSTRUCTION SET
Operation Flag
Z AC CY
× ×
× ×
799