Renesas RL78 Series User Manual page 476

16-bit single-chip microcontrollers
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RL78/G1D
Figure 13-67. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode)
transmission/reception data
No
Yes
Caution
Be sure to set transmit data to the SlOp register before the clock from the master is started.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Starting CSI communication
SAU default setting
Setting
Enables interrupt
Writing transmit data to
SIOp (=SDRmn[7:0])
Wait for transmission/reception
completes
Transfer end interrupt
Reading receive data
from SIOp (=SDRmn[7:0])
RETI
Transmission/reception
completed?
Yes
Transmission/reception
next data?
No
Disable interrupt (MASK)
Write 1 to STmn bit
End of communication
CHAPTER 13 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 13-63
(Select Transfer end interrupt)
Setting storage area and number of data for transmission/reception data
(Storage area, Transmission/reception data pointer, Number of communication data
and Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI).
Read transmit data from storage area and write it to SIOp.
Update transmit data pointer.
Start communication when master start providing the
clock
When transfer end interrupt is generated, it moves to
interrupt processing routine
Read receive data and write it to storage area. Update
receive data pointer.
Update the number of communication data and confirm
if next transmission/reception data is available
455

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