Renesas RL78 Series User Manual page 416

RL78/G1D
13.3.15 Noise filter enable register 0 (NFEN0)
The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin
to each channel.
Disable the noise filter of the pin used for CSI or simplified I
register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1.
When the noise filter is enabled, after synchronization is performed with the operation clock (f
2-clock match detection is performed. When the noise filter is disabled, only synchronization is performed with the
operation clock (f ) of the target channel.
MCK
The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the NFEN0 register to 00H.
Address: F0070H After reset: 00H
Symbol 7
NFEN0 0
SNFEN10
0
1
Set the SNFEN10 bit to 1 to use the R
Clear the SNFEN10 bit to 0 to use the other than RxD1 pin.
SNFEN00
0
1
Set the SNFEN00 bit to 1 to use the R
Clear the SNFEN00 bit to 0 to use the other than RxD0 pin.
Caution Be sure to clear bits 7 to 3 and 1 to "0".
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-21. Format of Noise Filter Enable Register 0 (NFEN0)
R/W
6 5
0 0
Use of noise filter of R
Noise filter OFF
Noise filter ON
D1 pin.
X
Use of noise filter of R
Noise filter OFF
Noise filter ON
D0 pin.
X
CHAPTER 13 SERIAL ARRAY UNIT
2
C communication, by clearing the corresponding bit of this
4 3
0 0 SNFEN10
D1 pin (RXD1/ANI16/SI20/SDA20/P03)
X
D0 pin (RXD0/TOOLRXD/SDA00/SI00/P11)
X
) of the target channel,
MCK
2 1
0 SNFEN00
0
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