Renesas RL78 Series User Manual page 165

RL78/G1D
Table 6-3. CPU Clock Transition and SFR Register Setting Examples (3/5)
(6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (B)
Remark The oscillation accuracy stabilization time changes according to the temperature conditions and the STOP
mode period.
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (D)
(8) CPU clock changing from subsystem clock (D) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
→
(D) (B)
Remarks 1. (A) to (J) in Table 6-3 correspond to (A) to (J) in Figure 6-16.
2. The oscillation accuracy stabilization time changes according to the temperature conditions and the
STOP mode period.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CSC Register Oscillation accuracy
HIOSTOP
0
Unnecessary if the CPU is operating with the
high-speed on-chip oscillator clock
CSC Register Waiting for Oscillation
XTSTOP
0
Unnecessary if the CPU is operating with the
subsystem clock
Oscillation accuracy
CSC Register
HIOSTOP
0
Unnecessary if the CPU is operating with the high-
speed on-chip oscillator clock
CHAPTER 6 CLOCK GENERATOR
CKC Register
stabilization time
18 µs to 65 µs
Stabilization
Necessary
stabilization time
18 µs to 65 µs
MCM0
0
CKC Register
CSS
1
CKC Register
CSS
0
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