Renesas RL78 Series User Manual page 279

RL78/G1D
(a) Timer mode register mn (TMRmn)
15 14
TMRmn
CKSmn1 CKSmn0
1/0 0
Operation clock (f
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0
TO0n
0
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0
TOE0n
0
(d) Timer output level register 0 (TOL0)
Bit n
TOL0
TOL0n
0
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0
TOM0n
0
Note TMRm2, TMRm4, TMRm6: MASTERmn = 1
TMRm0: Fixed to 0
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 7-76. Example of Set Contents of Registers
When Multiple PWM Output Function (Master Channel) Is Used
13 12 11 10
MAS
CCSmn STSmn2 STSmn1
TERmn
0 0 0
1
Note
Setting of MASTERmn bit (channels 2, 4, 6)
1: Master channel.
Count clock selection
0: Selects operation clock (f
) selection
MCK
0: Outputs 0 from TO0n.
0: Stops the TO0n output operation by counting operation.
0: Cleared to 0 when TOM0n = 0 (master channel output mode).
0: Sets master channel output mode.
9 8 7 6 5
STSmn0 CISmn1 CISmn0
0 0 0 0 0
Operation mode of channel n
000B: Interval timer
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
).
MCK
CHAPTER 7 TIMER ARRAY UNIT
4 3 2 1
MDmn3 MDmn2 MDmn1
0 0 0 0
Setting of operation when counting is started
1: Generates INTTMmn when counting is
started.
0
MDmn0
1
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