Renesas RL78 Series User Manual page 399

16-bit single-chip microcontrollers
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RL78/G1D
13.3.2 Serial clock select register m (SPSm)
The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register , and CKm0 is selected by bits
3 to 0.
Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1).
The SPSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears the SPSm register to 0000H.
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1)
Symbol
15
14
SPSm
0
0
PRS
PRS
mk3
mk2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Note
When changing the clock selected for f
so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array
unit (SAU).
Caution Be sure to clear bits 15 to 8 to "0".
Remarks 1. f
: CPU/peripheral hardware clock frequency
CLK
2. m: Unit number (m = 0, 1)
3. k = 0, 1
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-6. Format of Serial Clock Select Register m (SPSm)
13
12
11
10
0
0
0
0
PRS
PRS
mk1
mk0
f
CLK
0
0
f
2 MHz
CLK
0
1
f
/2
1 MHz
CLK
2
1
0
f
/2
500 kHz
CLK
3
1
1
f
/2
250 kHz
CLK
4
0
0
f
/2
125 kHz
CLK
5
0
1
f
/2
62.5 kHz
CLK
6
1
0
f
/2
31.3 kHz
CLK
7
1
1
f
/2
15.6 kHz
CLK
8
0
0
f
/2
7.81 kHz
CLK
9
0
1
f
/2
3.91 kHz
CLK
10
1
0
f
/2
1.95 kHz
CLK
11
1
1
f
/2
977 Hz
CLK
12
0
0
f
/2
488 Hz
CLK
13
0
1
f
/2
244 Hz
CLK
14
1
0
f
/2
122 Hz
CLK
15
1
1
f
/2
61 Hz
CLK
After reset: 0000H
R/W
9
8
7
6
PRS
PRS
0
0
m13
m12
Section of operation clock (CKmk)
= 2 MHz
f
= 5 MHz
f
CLK
CLK
5 MHz
10 MHz
2.5 MHz
5 MHz
1.25 MHz
2.5 MHz
625 kHz
1.25 MHz
313 kHz
625 kHz
156 kHz
313 kHz
78.1 kHz
156 kHz
39.1 kHz
78.1 kHz
19.5 kHz
39.1 kHz
9.77 kHz
19.5 kHz
4.88 kHz
9.77 kHz
2.44 kHz
4.88 kHz
1.22 kHz
2.44 kHz
610 kHz
1.22 kHz
305 Hz
610 Hz
153 kHz
305 Hz
(by changing the system clock control register (CKC) value), do
CLK
CHAPTER 13 SERIAL ARRAY UNIT
5
4
3
2
PRS
PRS
PRS
PRS
m11
m10
m03
m02
Note 1
= 10 MHz f
= 20 MHz f
CLK
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
4.88 kHz
2.44 kHz
1.22 kHz
610 Hz
1
0
PRS
PRS
m01
m00
= 32 MHz
CLK
32 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.3 kHz
15.6 kHz
78.1 kHz
3.91 kHz
1.95 kHz
997 Hz
378

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