Renesas RL78 Series User Manual page 739

RL78/G1D
22.3.1 Voltage detection register (LVIM)
This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well
as to check the LVD output mask status.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFFA9H
Symbol <7>
LVIM LVISEN
Note 3
LVISEN
0
1
LVIOMSK
0
1
LVIF
0
1
Notes 1. The reset value changes depending on the reset source.
If the LVIS register is reset by LVD, it is not reset but holds the current value. In other reset, LVISEN is
cleared to 0.
2. Bits 0 and 1 are read-only.
3. LVISEN and LVIOMSK can only be set in the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 =
1, 0). Do not change the initial value in other modes.
4. LVIOMSK bit is only automatically set to "1" in the timing below when the interrupt & reset mode is
selected (option byte LVIMDS1, LVIMDS0 = 1, 0) and reset or interrupt by LVD is masked.
● Period during LVISEN = 1
● Waiting period from the time when LVD interrupt is generated until LVD detection voltage becomes
stable
● Waiting period from the time when the value of LVILV bit changes until LVD detection voltage becomes
stable
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 22-2. Format of Voltage Detection Register (LVIM)
Note 1
After reset: 00H R/W
6 5
0 0
Specification of whether to enable or disable rewriting the voltage detection level
Disabling of rewriting the LVIS register (LVIOMSK = 0 (Mask of LVD output is invalid)
Enabling of rewriting the LVIS register (LVIOMSK = 1 (Mask of LVD output is valid)
Mask of LVD output is invalid
Mask of LVD output is valid
Supply voltage (V ) ≥ detection voltage (V
DD
Supply voltage (V ) < detection voltage (V
DD
CHAPTER 22 VOLTAGE DETECTOR
Note 2
4 3
0 0
register (LVIS)
Mask status flag of LVD output
Note 4
Voltage detection flag
), or when LVD is off
LVD
)
LVD
2 <1> <0>
0 LVIOMSK LVIF
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