Renesas RL78 Series User Manual page 394

RL78/G1D
Figure 13-2 shows the block diagram of serial array unit 1.
0
Peripheral enable
register 0 (PER0)
PRS
SAU1EN
113
f
CLK
Channel 0
Serial clock I/O pin
(when CSI20: SCK20)
(when IIC20: SCL20)
Synchro-
nous
detection
circuit
Output latch
(P20)
PM20
Noise
Synchro-
elimination
nous
enabled/
circuit
Serial data input pin
disabled
(when CSI20: SI20)
(when IIC20: SDA20)
SNFEN20
RXE
TXE
10 10
Channel 1
Serial clock internal I/O pin
(SCK21)
Serial data internal input pin
Synchro-
(SI21)
nous
circuit
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-2. Block Diagram of Serial Array Unit 1
Serial output register 1 (SO1)
0 0 0 0 0
CKO11 CKO10
Serial clock select register 1 (SPS1)
PRS
PRS PRS PRS PRS PRS
112 101
111 110 103 102
4
4
Prescaler
0 15 f /2 0 to
f /2 to f /2
CLK CLK CLK CLK
Selector
Selector
(Clock division setting block)
CK11 CK10
f
MCK
f
Edge SCK
Edge/
level
detection
CKS10 CCS10 STS10 SIS10
Serial mode register 10 (SMR10)
DAP CKP EOC DIR DLS DLS
10 10 10 10 101 100
Serial communication operation setting register 10 (SCR10)
CK11
Edge/level
Selector
detection
0 0
0 0 0 0
PRS
100
/2 15
Serial data register 10 (SDR10)
f
TCLK
Shift register
Communication controller
Mode selection
CSI20 or IIC20
(for transmission)
MD101 MD100
MD102
TSF
10
Serial status register 10 (SSR10)
CK10
Communication
controller
CSI21
CHAPTER 13 SERIAL ARRAY UNIT
SO11 SO10
Serial channel
enable status
SE11 SE10
register 1 (SE1)
Serial channel
SS11 SS10 start register 1
(SS1)
Serial channel
stop register 1
ST11 ST10
(ST1)
Serial output
SOE11 SOE10 enable register 1
(SOE1)
Output latch
PM14 or PM13
(P14 or P13)
Output
controller
Interrupt
Serial transfer end interrupt
controller
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
OVCT
10
Clear
Error controller
Error
information
BFF OVF
10 10
Serial data internal output pin
(SO21)
Serial transfer end interrupt
(INTCSI21)
Serial data output pin
(when CSI20: SO20)
(when IIC20: SDA20)
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